1. Field of the Invention
The present invention relates to static random access memory devices, and more particularly, to a static random access memory device having a single bit line configuration.
2. Description of the Background Art
A static random access memory (referred to as "SRAM" hereinafter) is used in various electronic devices such as computers. There is a strong demand for lower power consumption and increase in integration density in semiconductor memories as the functions of such electronic devices attain a higher level. Under such requirements, an SRAM having a single bit line configuration is conventionally known.
FIG. 55 is a circuit diagram of a memory cell for an SRAM having a single bit line configuration. The circuit of FIG. 55 is disclosed in a literature titled "16K CMOS/SOS Asynchronous Static RAM" (Digest of Technical Papers, pp. 104-105, 1979, IEEE, ISSCC). Referring to FIG. 55, the memory cell includes PMOS transistors Q21 and Q22, NMOS transistors Q23, Q24, and Q25, and diodes D1 and D2. A data storage circuit, i.e. a latch circuit is implemented by transistors Q21-Q24, and diodes D1 and D2. The data storage circuit is connected to a single bit line BL via an access gate transistor Q25. The gate of the transistors Q25 is connected to a word line WL.
In writing operation, the gate voltage of the transistor Q25 is boosted via the word line WL. Therefore, the transistor Q25 is turned on, whereby data determined by the potential cn the bit line BL is stored in the data storage circuit.
The memory cell of FIG. 55 is formed of five MOS transistors, whereby the occupying area on a semiconductor substrate can be reduced. However, the power consumption was great. For the purpose of reducing power consumption, the applicant of the present application has proposed the circuit configuration shown in FIG. 56.
FIG. 56 is a circuit diagram of a memory cell for a SRAM proposed previously by the applicant of the present invention. Referring to FIG. 56, the memory cell MC includes PMOS transistors Q31 and Q32 and NMOS transistors Q33 and Q34 forming a data storage circuit, and an NMOS transistor Q35 serving as an access gate. The data storage circuit 1 is connected to a single bit line BLj via the transistor Q35. The ground side of the data storage circuit 1 is connected to a source line SLj.
In writing operation, the word line WLi is boosted by a word line boosting circuit 307, whereby the gate voltage of the transistor Q35 is boosted. The transistor Q35 is turned on by a lower conductance, whereby data determined by the potential of the bit line BLj is stored in the data storage circuit 1.
When a column including a memory cell MC is not accessed, a source line potential control circuit 308 brings the source line SLj to an intermediate potential Vm (=VDD/2) in response to column address signals CA0-CAn. As a result, the supply voltage applied to the data storage circuit 1 is reduced to a half, so that the power consumed in the memory cell MC can be reduced.
Although the circuit configuration shown in FIG. 56 has the power consumption of the memory cell MC reduced by the function of the source line potential control circuit 308, it is necessary to charge/discharge the source line SLj according to whether the memory cell is accessed or not. Therefore, the power consumed by the charge/discharge of the source line SLj cannot be neglected.
Because the SRAMs shown in FIGS. 55 and 56 have the word line boosted in the writing operation, data writing may be carried out in other memory cells connected to the boosted word line even when not required. More specifically, the access gate transistors of the memory cells in other columns which should be not accessed have the gate voltage boosted, whereby the stored data is rewritten by the data (indefinite) determined by the potential of the bit line of that column.